226 lines
4.8 KiB
C++
226 lines
4.8 KiB
C++
#pragma once
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#include<hgl/TypeFunc.h>
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#include<hgl/CompOperator.h>
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namespace hgl
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{
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enum class SOCVendor
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{
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Unknow=0,
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Qualcomm, ///<高通
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Hisilicon, ///<海思
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Samsung, ///<三星
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MediaTek, ///<联发科
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Unisoc, ///<展锐
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Spreadtrum, ///<展讯
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JLQ, ///<瓴盛
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//Maxvell, ///<马维尔
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//Broadcom, ///<博通
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//TI, ///<德州仪器
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//Rockchip, ///<瑞芯微
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//Intel, ///<英特尔
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//nVidia, ///<英伟达
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//AMD, ///<AMD
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//Google, ///<谷歌
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ENUM_CLASS_RANGE(Unknow,JLQ)
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};
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constexpr const char *SOCVendorName[]=
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{
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"Unknow",
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"Qualcomm",
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"Hisilicon",
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"Samsung",
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"MediaTek",
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"Unisoc",
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"Spreadtrum",
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"JLQ",
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};
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const SOCVendor ParseSOCVendor(const char *str);
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enum class CpuArch
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{
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Unknow=0,
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ARMv7, ///<ARMv7
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ARMv8, ///<ARMv8
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ARMv9, ///<ARMv9
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MIPS,
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X86_32,
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X86_64,
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ENUM_CLASS_RANGE(Unknow,X86_64)
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};
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enum class ARMArch
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{
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Unknow=0,
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ARMv7, ///<ARMv7A
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ARMv8,
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ARMv8_2,
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ARMv9,
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ARMv9_2,
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ENUM_CLASS_RANGE(Unknow,ARMv9_2)
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};
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union ARMCpuName
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{
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//如A76，level为7,gen为6
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//A710，level为7,gen为10
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struct
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{
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char family; ///<A或X
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uint8 level; ///<级别,目前就0,1,3,5,7
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uint8 gen; ///<代数
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bool ae:1;
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bool c:1;
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};
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uint32 value;
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};
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/**
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* ARM CPU 核心信息
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*/
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struct ARMCpuCoreInfo
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{
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ARMCpuName name;
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ARMArch arch;
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bool support_32bit;
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bool support_64bit;
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};
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const uint32 ParseARMCpuName(ARMCpuName &,const char *); ///<根据字符串解晰ARM CPU名称ID
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bool ParseARMCpuCoreInfo(ARMCpuCoreInfo *,const uint32 &cpu_name_id); ///<根据ARM CPU名字ID解晰CPU信息
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enum class KryoArchLevel
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{
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Prime,
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Gold,
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Silver,
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ENUM_CLASS_RANGE(Prime,Silver)
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};
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/**
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* ARM CPU簇信息<br>
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* 注：这里的频率单位为MHz，而且只是默认频率，实际频率可能会更高或更低
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*/
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struct ARMCpuClusterInfo
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{
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ARMCpuCoreInfo arm; ///<对应的ARM核心信息
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uint core_count; ///<核心数量
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uint base_freq; ///<基础频率
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uint boost_freq; ///<最高频率
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};
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struct SOCInfo
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{
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SOCVendor vendor;
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char model[32];
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public:
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CompOperatorMemcmp(const SOCInfo &);
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};
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/**
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* 根据收集到的SOC信息，解晰具体的SOC厂商和主要型号
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*/
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bool ParseSOCInfo(SOCInfo &,const char *);
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enum class SOCGPUVendor
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{
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Unknow=0,
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PowerVR,
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Mali,
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Adreno,
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Vivante,
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Intel,
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Radeon,
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Tegra,
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Maleoon,
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ENUM_CLASS_RANGE(Unknow,Maleoon)
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};
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constexpr const char *SOCGPUVendorName[]=
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{
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"Unknow",
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"PowerVR",
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"Mali",
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"Adreno",
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"Vivante",
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"Intel",
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"Radeon",
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"Tegra",
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"Maleoon",
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};
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const SOCGPUVendor ParseSOCGPUVendor(const char *str);
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struct SOCGPUInfo
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{
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SOCGPUVendor vendor;
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char model[32];
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uint core_count;
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uint freq;
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public:
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int Comp(const SOCGPUInfo &info)const
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{
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int result;
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result=int(vendor)-int(info.vendor);
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if(result)return result;
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result=strcmp(model,info.model);
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if(result)return result;
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return core_count-info.core_count;
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}
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CompOperator(const SOCGPUInfo &,Comp);
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};
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/**
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* SOC 产品信息
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*/
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struct SOCProductInfo
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{
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char product_name[64]; ///<产品名称
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SOCInfo soc_info; ///<SOC基本信息
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SOCGPUInfo gpu_info; ///<GPU信息
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uint cpu_cluster_count; ///<CPU簇数量
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struct
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{
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char core[32]; ///<CPU核心名称
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uint count; ///<核心数量
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float freq; ///<频率
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}cpu_cluster[4]; ///<CPU簇信息
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};//struct SOCProductInfo
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}//namespace hgl
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